CLOCK Recovery Circuit Based on Preset Counter
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
In a 2 Mbps clockless network the receive clock signal must be derived from the received data stream. This is a clock recovery circuit which has two functional parts, i.e., an elastic clock and a synchronizer. The elastic clock can produce a nominal cycle of 500 ns, a stretched cycle of 560 ns and a shrunk cycle of 440 ns. Each time there is a positive-going transition on received data signal RD, the synchronizer compares the clock cycle to this transition and defines the length of the next clock cycle to cause synchronization with the data. The clock includes a presettable counter 10. This counter counts up in sequence (at a given CK cadence of, for instance, 16 MHz) until a "load" signal is active. The timing decoder 12 is made to generate the load signal when a count of B (hexadecimal) is reached.