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I/O Address Remap Via Dual-Map Segmentation Registers Disclosure Number: IPCOM000061434D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

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Bhansali, M Bourke, D Brinck, G Downs, E Hallerman, M Kurtz, H Rawson, F Taylor, G [+details]


A method is described that utilizes segmentation registers for the input/output (I/O) devices of the IBM Series/1 processor to enable them to address more than the upper limit of physical storage when extended storage architecture is provided. Currently, Series/1 processor I/O devices are limited to 512 KB of addressing. When extended storage is available, such as up to 16 megabytes (MB), an effective method to expand the 512 KB Series/1 address into the 16MB addressing range is needed. To minimize software impacts and to maintain I/O device compatibility, the Series/1 DCB/IDCB I/O control structure is maintained. Thus, the architecture is limited to eight I/O address keys. For information, reference is made to the article on page 968 of this issue. A related feature is described in the article on page 977.