Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
A simple single-input polarity-hold (PH) latch, which is shown in Fig. 1, has the potential for being reused as part of more complex latch functions. This allows a simple latch design to service the logical needs of an entire chip or an entire circuit family. The following describes a SET-RESET (SR) and a J-K Latch designed in this manner. Fig. 2 gives the schematic of the SET-RESET Latch. The simple polarity-hold latch is shown with its two inputs: Data and Clock. The RESET line drives the Data port of the PH latch, and the output of the four-device input circuit drives the clock port. The four-device input circuit will enable the PH latch clock input as long as RESET and SET are not both equal to '1'. If either R or S is not equal to '1', the state of the latch can change as a function of R on the data port.