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Differential CMOS Logic Circuit With an Efficient Load Means

IP.com Disclosure Number: IPCOM000061446D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Davis, JW Thoma, NG [+details]

Abstract

This article describes a circuit arrangement wherein the class of logic known as differential cascode current switch (DCCS) logic can be directly mapped into complementary metal oxide semiconductor (CMOS) technology by replacement of the output load resistors with appropriately connected P channel field-effect transistor (FET) devices and the NPN logic transistors can be directly replaced with N channel field-effect transistors. In conventional CMOS circuit implementation, the logic decoded in the P channel load devices is the dual of the logic performed by the N channel devices. One half of all the active devices in any logic net are used strictly as load devices that don't really perform useful logic but merely keep standby power at zero [*].