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Single Logic Cell Test Latch for AC Testing of Embedded Arrays

IP.com Disclosure Number: IPCOM000061482D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Torku, KE Tuminaro, AD [+details]

Abstract

High performance embedded arrays require accurately measured AC timings during test. Read Access Time measurements, in particular, are unduly influenced by receiver and driver delays which are added to the performance of the RAM (random-access memory). By use of the test latch described in this article, access times may be determined without these complications, thereby greatly increasing the accuracy of measurement. Referring to Fig. 1, a test latch TL is used between the array AR and the driver DR, to latch the output data before going to the driver. An array data output signal DO can be used to set the latch, and an external test clock signal TC can be used to prevent the latch from changing. If the array data output signal occurs before the specified clock reset signal, then the access time is acceptable.