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Simulated Stress Tester Assembly

IP.com Disclosure Number: IPCOM000061516D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Carden, TF Engle, SR [+details]

Abstract

This test assembly simulates the module environment of a thermally enhanced integrated circuit (IC) chip which is surface mounted to a chip carrier by controlled collapse chip connections (C4). It provides for the measurement of forces and stresses which would be experienced by the chip and hence its C4 connections in its prototype module environment. In the assembly 10, the module environment is simulated by the pinned ceramic substrate S, module cover C and a known quantity of thermal grease (not shown) which is placed in the space under the cover C. A sample chip (not shown) is located in the environment and is mounted to a stainless steel plate P. Alternatively, the plate P itself may be used to simulate the chip.