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Prevention of Unknown States (Indeterminate Data) in Multi-Port Arrays During Random Pattern Testing

IP.com Disclosure Number: IPCOM000061532D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Dennison, RT Fields, DB Freeman, LB Muench, PD Stinson, WF [+details]

Abstract

If two Write ports of a multi-port array write the same address, a race condition can exist which will cause indeterminate data to be stored in the array. Such a condition occurs when random pattern test generation methods are employed in testing logic chips, modules and systems. The scheme disclosed in this article eliminates the race problem and allows the efficient random pattern testing of chips with multiple write port arrays. Fig. 1 illustrates a clock chopper (CC) macro supplying required writing pulses to a multi-port array having one write port. Fig. 2 shows a clock chopper generating two write pulses for a multi-port array having two write ports. The pulses are generated from a positive-going clock pulse edge at the pre-driver block 1. Time delay circuit blocks 2 and 3 delay the output of 1.