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Off-Chip Power Supply Decoupling Via N-Well Disclosure Number: IPCOM000061538D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

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Penoyer, RF [+details]


This article describes a technique for utilizing the complementary metal oxide silicon (CMOS) technology n-wells to supply the high on- chip currents of short duration (WI's) from a low impedance on-chip source. The inherently large capacitance between n-well and substrate provides a ready-made on-chip charge source which may be used to sink high current spikes of short duration which appear on a chip power supply (VH) bus. Fig. 1 shows an n-well structure 10 needed in the CMOS n-well technology for p-channel devices 11. The n-well bias (VNW) of approximately + 6 volts and substrate bias (VSUB) of approximately - 1 volt are needed to prevent forward biasing of the p-channel junction of device 11, resulting in latch-up with a supply voltage (VH) of approximately + 5 volts.