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Allowing Orderly Shutdown of a System Disclosure Number: IPCOM000061544D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

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Geiger, SP Sutton, AJ [+details]


This polling scheme allows the processor controller (PC) to select between different possible options when it detects the possibility of an error between the central electronic computer (CEC) and the PC. When the PC detects an error, it has one of two options. It can place the CEC in the system checkstop state, or it can disable the response to the last poll of the CEC to PC polling mechanism, and as a result the CEC will invoke a machine check.