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Scan String FLUSH Test for Product Performance Disclosure Number: IPCOM000061545D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

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Gargiulo, NT [+details]


This article describes a technique for using shift register latch (SRL) strings in a logic chip design where level sensitive scan design (LSSD) ground rules are used to measure process-induced AC chip performance variations, to correlate measured results with precalculated delay data to predict chip functional performance and to use that correlation as the basis for a performance measurement test. Performance of a logic chip is limited by delays associated with the worst-case critical path which is defined as the longest functional path through a chip. By correlating the measured stage delays in a sample string of circuits on a chip with precalculated delay data, expected performance of a product chip can be established.