Browse Prior Art Database

Process for Trench Planarization

IP.com Disclosure Number: IPCOM000061547D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Chiu, TY Li, GP [+details]

Abstract

This article relates generally to integrated circuit fabrication and, more particularly, to a method of planarizing refilled isolation or storage capacitor trenches. Improved etching control of refilled trenches is obtained by establishing an oxide reference plane, since planarization is in dependent of non-uniformity in both trench etching and amount of refilled material. This process is applicable to trenches refilled with either polysilicon or epitaxial silicon. Referring to Fig. 1 and the process for leveling polysilicon, a silicon wafer 1 having a recess oxide layer 2 has deposited thereon layers of nitride 3, oxide 4, nitride 5, oxide 6 and polysilicon 7. Low pressure chemical vapor deposition is used for the nitride layers 3 and 5 while conventional chemical vapor deposition is used for the oxide and polysilicon layers.