Zero-Fetch Cycle Branch
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
This article describes a technique utilizing an address counter synchronization algorithm which allows implementation of a zero-fetch cycle branch in a pipelined processor. This algorithm increases performance by eliminating one cycle from the execution of branch instructions. As branch instructions account for a large percentage of most instruction mixes, optimization of branch instruction execution is a vital performance objective of any processor design. Branch performance is especially crucial in a pipelined processor, since such a processor attempts to achieve single-cycle instruction execution. A single-chip implementation of a processor and its storage control makes it possible to implement the processor and its instruction cache on a single chip.