Multilevel CMOS Sense Amplifier
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
A CMOS sense amplifier is described which detects multilevel voltages on a data line of a storage array and translates the voltage to a logical (binary) signal. Chip density may be increased by storing multiple data bits on a single line, i.e., two data bits can be represented by one of four voltage levels on a single line. In sensing the multiple levels the circuit takes advantage of the availability of P and N channel devices. The sense amplifier circuit, shown in the figure, can detect multiple signal levels and simultaneously reconstruct by means of appropriate logic the corresponding data bits. The data line and internal nodes A, B and C are biased high and nodes D and E are biased low by means of static and/or dynamic load devices.