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Low Power BIFET Circuit Disclosure Number: IPCOM000061563D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

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Klimanis, VD Montegari, FA Swietek, DJ [+details]


A design has been proposed that uses N metal oxide semiconductor (NMOS) and PMOS devices instead of resistive loads in a logic circuit. The combination of field-effect transistor (FET) and bipolar devices can produce a high speed logic inverter with very high input impedance, high current sink capability, active pullup and zero power dissipation in the off state. The low power BIFET (LPB) circuit shown in the drawing uses PFETs connected as source followers to provide a NAND logic function followed by a bipolar inverter with NFETs to supply the base drive and PFET, collector pullup devices. The PFETs T3 and T4 are used as source-follower logic gates which provide very high input impedance and which do not require current sinking by the driving circuit. The base current for the bipolar transistor is provided by NFETs T1 and T2.