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LSSD Testable Four-Port Register

IP.com Disclosure Number: IPCOM000061568D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Donze, RL Luick, DA Skuldt, EL Verheul, JM [+details]

Abstract

Many computer systems have data flow logic implemented with level sensitive scan design (LSSD) which is testable in a manner set forth in U. S. Patent 4,268,902. The 4-port register designed using LSSD is not only testable but offers a density advantage over standard TTL (transistor-transistor logic) latches. The register has two input and two output ports which can operate simultaneously. The register bank (Fig. 3) is constructed in the following manner: . L1 latches (standard polarity hold L1 latches) are used to construct two 18-bit registers. . The +L1 output of one of these registers is used to drive the port1 data input of the register bank, and the +L1 output of the other L1 register is used to drive the port2 data input of the register bank. .