Enhanced Electrostatic Discharge Buffer Network
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09
Superior protection of integrated circuit devices from electrostatic discharge (ESD) damage is achieved in chip layout design by the placement of an ESD buffer network in very close proximity to all chip pads. A preferred ESD buffer network includes a first voltage divider circuit having a first resistor serially connected with a thick oxide field- effect transistor (FET) with grounded gate and a second voltage divider circuit having a second resistor serially connected with a thin oxide device, one end of the second resistor being connected to a control electrode of a transistor which is to be protected. Advantage is taken of existence of parasitic bipolar devices associated with the FET devices.