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Split Emitter CTS Memory Cell

IP.com Disclosure Number: IPCOM000061574D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

A small, fast memory cell type, which offers an improved access time at a higher density than that obtainable from the conventional CTS (complementary-transistor switch) cell, is described in this article. CTS-type memory cells, employed in high performance memory arrays, commonly use two groups of merged transistors (cross-coupled) to provide the flip-flop, while requiring two other devices for Read-Write coupling. These Read-Write devices may be eliminated by employing the split emitters of the flip-flop to accomplish the Read-Write couplings, with benefit to cell density (reduced cell size). The disclosed split emitter complementary-transistor switch (SECTS) cell circuit and an accompanying cell layout sketch are shown in Fig. 1, where the transistor emitter, collector and base are respectively identified by E,C and B. Fig.