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Device Interconnect Scheme for Vlsi

IP.com Disclosure Number: IPCOM000061576D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Hargrove, MJ White, FR [+details]

Abstract

This article features a technique for interconnecting field-effect transistor (FET) device gate electrodes to source or drain diffusions by etching through a single photomask without degrading the diffusions. Fig. 1 shows a cross-section of an FET 10 with a source diffusion 11, a drain diffusion 12, a gate electrode 13 and an electrode spacer 14. Fig. 2 shows the deposition of an interconnect material 15 followed by the deposition of a silicon nitride (Si3N4) film 16. The interconnect material 15 is an oxidizable conductor, such as polysilicon. Fig. 3 shows a Si3N4 film mask segment 17 defined by a photomask 18 where the interconnect from the gate electrode 13 to the source diffusion 11 is to occur. (Polysilicon to polysilicon and diffusion to diffusion interconnects are possible over thick oxide.