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Memory Cells With Resistor Clamps

IP.com Disclosure Number: IPCOM000061578D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

This article suggests the use of an inverse transistor clamp to prevent deep saturation of memory cells in semiconductor devices. When clamped, the cells will operate in pseudo-saturation mode with cell stability improved. Bipolar random-access memory (RAM) cells with Schottky barrier diode (SBD) clamps are sensitive to a-particle disturbs. If the clamps are removed to enhance the a-particle related stability, the ON transistor goes into saturation. This saturated condition results in a slower write time and bigger write time tolerance. A beta lowering implant used to improve the write performance requires an extra process step, and read access may be slowed.