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Sample and Hold Circuit

IP.com Disclosure Number: IPCOM000061582D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Trnka, JT Wu, PT [+details]

Abstract

A new bipolar sample-and-hold circuit featuring a low droop rate and fast acquisition time. The sample-and-hold (S/H) circuit is shown above. An external sample-and-hold capacitor is connected to node 30. By connecting a unity gain amplifier OP1 to node 30, a sample-and-hold amplifier is formed. Q19-Q22, Q28, Q30-Q34 comprise a TTL receiver that places the S/H in either the sample or hold mode.