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Differential Latched Receiver Circuit

IP.com Disclosure Number: IPCOM000061611D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Gaudenzi, GJ Ippolito, PM Kikuchi, D Tempest, SL [+details]

Abstract

This article describes a general-purpose receiver circuit containing a built-in latch function. During operation, transistors Q1A, Q1B and Q3 function as a general-purpose differential receiver with the input threshold being set by the reference voltage VR. Transistors Q2A and Q2B are collector- dotted into the circuit, and they will latch the input signal once the current source I2 is enabled. For proper operation, the current sources I1 and I2 must be sequenced, that is, I2 must be activated before deactivating I1. Once I1 is deactivated, the latch becomes immune to the signal on the input line. Note: The required anti-saturation clamps are not shown.