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Combining of Consecutive Processor Stores

IP.com Disclosure Number: IPCOM000061616D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Brandt, HR Gannon, PM Marchini, TR [+details]

Abstract

Back-to-back store requests from a CPU which constitute the even and odd doublewords of a quadword may be serviced as a single write operation in the next lower level in the storage hierarchy. Store-through CPU designs commonly send each processor store data unit from the cache to the next level of the memory hierarchy. The bandwidth required of the memory is often a function of the anticipated store-type activity and becomes a problem when CPU cycle times improve at a faster rate than memory cycle times. It is therefore desirable to reduce the store traffic to the memory in order to conserve memory bandwidth for line fetches and channel requests. This problem can be reduced by combining the data units of two successive processor store requests to the next level in the memory hierarchy into a single store operation.