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Minimized Implementation for a Digital Data Clock Extraction and Synchronization

IP.com Disclosure Number: IPCOM000061630D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Chliwnys, A Dimitri, KE [+details]

Abstract

The function consists of synchronizing data variation to a clock period. It provides the capability to synchronize "Ones" data to clock by correcting its own clock period by "1/11th" for that period, on the fly (Fig. 1). The implementation consists of an advance and retard Johnson counter. The counter samples the clock period at an odd number of intervals. In this embodiment, the sample is "11". The sample count advances or retards by one sample or "1/11th" of the clock period, with respect to "Ones" data leading or lagging. No corrections are made for "Zeros" data or when data is in sync with the clock period. The Johnson counter consists of 6 polarity hold latches or SRLs (Shift Register Latches for LSSD) Modulo 12 count (Fig. 2). NRZI data is converted into RZ data and then sampled by the counter.