Invalid Address Protection for Computer Systems With Extended Memory Addressing
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
A technique is described whereby invalid address protection provides a means of insuring that only the addresses necessary to enable extended addressing of computer programming will be implemented. A program check interrupt handler is provided in conjunction with a segment identifier to signal the following conditions: a) Invalid Effective Address bit - If bit 0 of any processor effective address is 0 and the program is running in problem state, or if bit 0 of an instruction address changes during the computation of a jump address, a program check will occur with the extended processor status word (EPSW) bits 01 and 06 set on. b) Invalid Address Space - If bit 0 in the address space array entry pointed to by an active segment identifier is off, this specifies that an invalid address space has occurred.