Translated Address Cache in Computer Systems With Extended Memory Addressing
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
A technique is described whereby a translated address cache is provided in computer systems with extended addressing capabilities so as to eliminate the need to access memory segment tables in determining the real page address, in addition to the required data access. The translated address cache is inserted in the memory control section of the extended addressing unit, as shown in the figure. Since the address translation algorithm (see page 1478) requires that two storage accesses be made for each instruction or operand access, the use of a cache mechanism eliminates additional accesses to storage for a high percentage of store requests. The translated address cache is unique in that it operates in parallel with the logical-to-physical address translation mechanism.