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Interrupts and Level Switching for Computer Systems With Extended Memory Addressing

IP.com Disclosure Number: IPCOM000061646D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Kurtz, HL Pipitone, RM Wyatt, VD [+details]

Abstract

A technique describes the way interrupts and level switching are handled when the IBM Series/1 computers are equipped with extended addressing capabilities. A system running in extended mode handles interrupts in the same way as in compatibility mode with the following differences: Address Space Selection - In compatibility mode, Address Key 0 is used to invoke the proper interrupt handler program. In extended addressing mode, one of two address spaces is chosen as a function of the type of interrupt. All I/O interrupts are vectored using system identifier (SID) zero. Class interrupts are vectored using either SID 0 or the System SID in the active extended level status block (ELSB). Determining which SID is used is a function of the specific class interrupt.