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Low Power Decoding Scheme for Partitioned Arrays Disclosure Number: IPCOM000061665D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

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Related People

Kilmer, CA Parent, RM [+details]


This article describes how some capacitive discharge and charge current may be eliminated in unselected arrays of a partitioned field-effect transistor-dynamic random-access memory (FET-DRAM). To reduce active select power and improve performance, DRAM designs are frequently partitioned into two or more sections. In these designs, one section is selected while the other sections remain in standby. The standard approach is to decode pulses driving the selected section and leave the remaining sections without powered pulses. All section word and bit decoders are activated by one set of address lines and only one section is selected. As a result, power is wasted due to the charging and discharging of decoders in the unselected sections on each select cycle. In operation of a standard decode circuit as shown in Fig.