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Method to Reconfigure Logic Signal Paths

IP.com Disclosure Number: IPCOM000061699D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Busch, RE Redman, TM Thoma, EP [+details]

Abstract

A method of reconfiguring logic trees by means of personalization using fuse decoding is disclosed. A specific implementation of the method is address steering in a random-access memory (RAM) where either normal or redundant elements are used without an access penalty. As memory data rates continue to be shortened, any additional delays encountered by redundancy schemes become intolerable. By steering a fuse-programmed address to a redundant circuit column in a RAM, the redundant column is enabled. Also, by permanently disabling a replaced address so that the results of a compare circuit are not in the access path, the delay encountered is confined to the R/C delay of address-steering transistors. Fig. 1 shows a block diagram of the redundancy scheme for a RAM.