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Partial Tree of Cascode Emitter Coupled Logic

IP.com Disclosure Number: IPCOM000061715D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

A partial logic tree is described in this article which reduces the number of devices and wirings required in logic design while allowing an increase in the number of functions available per circuit. Fig. 1 illustrates a general representation of a CECL (cascode emitter coupled logic) circuit in which F0 and F1 are the Boolean functions to be realized. Inputs may be in true/complementary (T/C) pairs or in single rails, and level clamps may be provided in parallel with pull-up resistors R0 and R1 to prevent transient saturation. For any input state, one and only one current path is formed from either R0 or R1, through the current switch network (CSN) to the current drain at the bottom.