Scan Methodology on CMOS Products
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09
In European Patent Application No. 83430043.6 (Publication Number 146661), a methodology has been disclosed to diagnose failures occurring in LSSD (Level Sensitive Scan Design) chains. This method was based on DC variations induced on Idd supply current during the loading of the chain. Nevertheless, this method was not applicable on CMOS products because the global consumption of a CMOS chip is theoretically null. Since then, this method has been successfully adapted to CMOS and diagnostics can be run on this family now. Basically, the NMOS method consisted in measuring the supply current value before and after the switching of each latch of the chain. The rational is that each time a latch switches, some transistors turn on or off inside the latch and in the circuits driven by the latch.