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Exhaustive Test of a Bus Interface Disclosure Number: IPCOM000061754D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

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Orengo, G Picon, J Pin, C Poiraud, C [+details]


A processor P (Fig. 1) is connected to adapters A1...An, by a bus through a redrive card R. This bus is composed of 3 parts. -Tags out from P to adapters. -Tags in from adapters to P. -Data (2 bytes) which are bidirectional. The data transfer protocol is done via the tag lines. Checkers are implemented in the interface part I of P. They verify data parities and tag sequencing, and generate return codes to P according to the checkings results. For reliability purposes, all the checkers must be verified at the machine Initial Program Loading (IPL). To do that, the processor, which is already master of the tags out and the data (in outbound transfer), must be able to drive also the tags in, which are under adapter control.