Browse Prior Art Database

Array Power Down Scheme

IP.com Disclosure Number: IPCOM000061760D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Chan, YH [+details]

Abstract

This article describes a means for powering-down the stand-by current of a bipolar memory cell to enable low current stress testing. Bipolar memory cells such as Complementary-Transistor Switch or Harper-PNP types are sensitive to leakages and device degradation due to their low current attribute. To improve the reliability of the chip, in arrays using such cells, it is desirable to have a circuit means on-chip to power down the memory cells for stress testing. Power-down circuitry enables the array's stand-by current to be switched from its normal value to a lower, predetermined magnitude (e.g., an order of magnitude lower). Operating at a reduced current level, the memory cells are stressed for low current leakage sensitivity.