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Technique for Performing Module-Level Automated Testing for CMOS Latch-Up

IP.com Disclosure Number: IPCOM000061773D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
McLean, JG [+details]

Abstract

A technique is described whereby semiconductors which are fabricated using complementary metal-oxide silicon (CMOS) technology are automatically tested for latch-up susceptibility. The test is unique in that an automated tester used to detect latch-up characteristics of CMOS semiconductors has the ability to remove power from the semiconductor as soon as a latch is detected, so as not to destroy the semiconductor during the test. Furthermore, the technique allows rapid sequential testing at multiple pin locations without fear that damage to previously tested pin locations will affect results.