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Concurrent Master-Slave Serial BUS Controller

IP.com Disclosure Number: IPCOM000061792D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Chausanski, G Krieg, ML Thomas, KG [+details]

Abstract

One of a plurality of microprocessors connected to a serial bus can have one or more slave microprocessors connected thereto and communicate therewith while maintaining an active link on the bus with the other microprocessors. This decreases the traffic from the bus. A plurality of microprocessors 1, 2, 3, and 4 (Fig. 1) are connected electrically with a bit serial asynchronous bus using three signals. These signals are GND, BUS, and BRQ*. The GND signal is connected over a common line 5 and is the logic ground used to establish an electrical voltage level. The BUS signal is supplied over a line 6 and is a bidirectional signal on which the serial bit stream is transmitted and received.