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CMOS Driver With Output Level Control

IP.com Disclosure Number: IPCOM000061798D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Kim, IW [+details]

Abstract

A CMOS driver circuit for general-purpose interfacing is described which provides accurately controlled up-level voltage output while maintaining high performance. The circuit shown in Fig. 1 is comprised of conventional off-chip drivers (OCDs) for the true (transistors 12 through 17) and complement (transistors 5 through 10) inputs. Transistors 11 and 18, plus the capacitive load C1, complete the conventional CMOS driver circuit. The addition of the NAND circuit (transistors 1, 2, 3, 4, 19 and 20) plus the pair of resistors R1 and R2 provide the desired control of the up level of the output data "out" with no degradation in driver performance. A negative-going complement signal at Comp. results in the signal at node n1 being passed through the NAND circuit (transistors 1, 2, 3, 4, 19, 20) and driving transistor 9, as usual.