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Computational Efficiency of Two-Operand Adders

IP.com Disclosure Number: IPCOM000061820D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Sinha, B [+details]

Abstract

This article describes a method to determine the efficiency of two- operand adders. Given the requirement of an n-bit adder, the most efficient algorithm can be chosen by utilizing this method. The existing method for obtaining the efficiency of two-operand adders is explained in [*]. The method disclosed herein proposes a new measure of efficiency of two-operand adders in today's technology and compares some of the standard adders used in present arithmetic logic unit (ALU) designs. This method has been developed with the following two guidelines in mind: 1. Efficiency , however formulated, is only good as a relative measure. 2. Efficiency should be simple, and convey some meaningful means of comparison between schemes for achieving similar processes, i.e., between various adder schemes.