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Polysi-Si3n4 Emitter-Base Spacing Definition

IP.com Disclosure Number: IPCOM000061845D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Antipov, I [+details]

Abstract

A method has been proposed to more accurately etch thin films in the production of transistors thereby reducing the etching of Si in the emitter. It proposes the use of polysilicon (PolySi) instead of tetraethyl orthosilicate (TEOS) for sidewall formation. In the conventional sidewall formation process Si may be etched in the emitter opening due to the lack of selectivity between Si3N4 and SiO2 . This is because there is difficulty in obtaining gasses that reactive ion etch (RIE) SiO2 but not Si3N4 . Hence, during RIE of the thick layer of chemical vapor deposition (CVD) SiO2, Si3N4 may also be removed unintentionally. This may result in Si in the emitter area being removed in a subsequent RIE.