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Set Clocks for CMOS Drams

IP.com Disclosure Number: IPCOM000061851D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Parent, JM Scheuerlein, RE [+details]

Abstract

In order to set a cross-coupled dynamic random-access memory (DRAM) sense amplifier optimally, a set clock circuit is described which wave-shapes signals on common source nodes of latches to maintain zero overdrive on "off" devices, thereby maintaining maximum available drive on active devices. CMOS DRAMs utilize an N-latch for initial setting and a P-latch to pull the high bit line to supply potential Vdd. This allows the bit lines to be referenced to Vdd/2 for power reduction; however, the sense amplifier drive is reduced at sense time which emphasizes the importance of maintaining maximum available drive on active devices. In Fig. 1, a typical CMOS DRAM bit line (BL) cross-section is shown comprised of a P-latch, transistors T1p and T2p, and an N-latch, transistors T1n and T2n. Bit lines BL and BL are referenced to Vdd/2.