Browse Prior Art Database

Reconfigurable Single/Dual Port RAM System

IP.com Disclosure Number: IPCOM000061853D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Schoenike, RL [+details]

Abstract

A system, which includes two RAM circuits on a single chip for internal register storage, can be configured as a single port configuration or as a dual port configuration memory system. In the dual port configuration, the RAM circuits operate as a single memory system and allow two words to be read simultaneously from the memory system. In a single port configuration the RAM circuits can be addressed independently which facilitates the enlargement of data storage. Referring to the figure, a memory system 10 includes a micro-instruction register 12 and a decode circuit 14. A central processing unit determines which mode memory system 16 should be configured and then generates the proper micro-instruction. The micro-instructions are fed to register 12 and decoded by circuit 14.