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Novel Method of Attaining High Etch Selectivity Using Intrinsic Polysilicon Disclosure Number: IPCOM000061856D
Original Publication Date: 1986-Sep-01
Included in the Prior Art Database: 2005-Mar-09

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Polavarapu, MS Stanasolovich, D [+details]


A process has been developed which will allow the use of present polysilicon RIE (reactive ion etch) processes for the fabrication of smaller devices with thinner gate electrodes. Referring to Fig. 1, a silicon substrate 10 having a gate silicon dioxide layer 12 has an intrinsic polysilicon layer 14 deposited thereon. This intrinsic polysilicon layer 14 is then coated with a hard masking material 16, which can be silicon dioxide, UV-hardened photoresist, multilayer resist, aluminum, etc. This hard masking material 16 is then patterned using conventional lithographic techniques to define the gate structure. Arsenic, or a similar N+ dopant, is then implanted in the intrinsic polysilicon layer 14 throughout its depth, as seen in Fig. 2.