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Cmos Hysteresis Receiver Disclosure Number: IPCOM000061861D
Original Publication Date: 1986-Aug-01
Included in the Prior Art Database: 2005-Mar-09

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Wissel, L [+details]


A receiver circuit is described which achieves switching voltage hysteresis required for noise immunity in a simple and easily analyzed configuration. This circuit receives a non-complementary metal oxide semiconductor (non-CMOS) level, e.g., transis transistor logic (TTL) or a lower General Purpose Interface (GPI) input signal Vin and translates it to a CMOS level output signal Vout. The receiver employs a linear differential amplifier (LDA), a voltage divider, transistor TR1 and TR2, which establishes a reference voltage Vref, and a transistor Tr which alte the characteristics of the voltage divider to cause Vref to switch between desired high and low hysteresis switchpoint voltages.