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Common Tester for Multiple Array Chip Configuration

IP.com Disclosure Number: IPCOM000061892D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Cheng, FM Zvaigzne, G [+details]

Abstract

Failures in a memory using any array chip geometry can be found without changing the testing hardware in the storage control element (SCE) for the memory if the address register (Hamtsar) used by the hardware is controlled by a separate mask register (HAMR) of the same size as the address register.