Virtual Interrupt Mechanism
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
The mechanism set forth provides the ability to define a mapping of arbitrary (software and hardware) interrupts into action routines for each distinct program environment. A queued hardware interface is used, thus avoiding the need to DISABLE interrupts. Also, the need for first level interrupt handlers (FLIHs) and second level interrupt handlers (SLIHs) is avoided. This implies higher performance and better CACHE hit ratios. Equally important, this mechanism is used as a means for inter-processor communication, where the requester is not aware of whether the receiver is on the same processor or a different one. Thus, the requester does not have to code alternative logic in its mainline paths depending upon whether a call is to be made on the same processor or on a different one.