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Selection Scheme for MTL Cells With Split Emitters

IP.com Disclosure Number: IPCOM000062036D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

This article is directed to a means for enhancing the performance (by reducing the cycle time) of existing MTL (merged transistor logic) selection schemes by partitioning the Word Lines and Bit Lines in such a manner as to remove the need for a discharge/restore process in the selection cycle. The object of the disclosed selection scheme is to isolate the Source Line of a group of bits so that the diffusion capacitances of the unselected cell injectors do not interfere with the Source Line (SL) selection. This is possible only after the cell circuits are rearranged. As shown, cell injectors are connected to a common Source Line, and the split bottom emitters of the inversely operated transistors are tied to the left and right Bit Lines (BLs and BRs).