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Self-Test N-Stream Online Isolation Disclosure Number: IPCOM000062071D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

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Smith, GL [+details]


Utilizing an n-stream simulation program, which can have performance as much as n times as fast as a conventional simulator provides a practical process for identifying the first failing self-test pattern even in the presence of large circuit counts, large pattern counts, and arrays in the hardware under test. It is the speed of the n-stream simulator which makes the processor practical for large logical entities. Means must be provided for extracting the value of all latches and arrays in the hardware under test. Typically, scan paths are used for this purpose. Also, means must exist for loading latches with reproducible pseudo-random patterns and for compressing latch values into accessible signature registers.