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Decimal Parity Prediction

IP.com Disclosure Number: IPCOM000062079D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Curran, BW [+details]

Abstract

OVERVIEW A method to predict the parity of a decimal sum or difference is described. It differs from other prediction schemes in that only two parities are predicted for each digit position. The additional circuitry to implement this prediction is not excessive. It can easily be designed to also predict the parity of a binary addition. BACKGROUND Single-bit errors in an adder can be detected by comparing the predicted parity of an addition/subtraction with the actual parity of that operation. All single faults within a circuit are detectable if each single fault creates (at most) a one-bit error in the result. To reduce the delay through a multi-byte decimal (or binary) adder, two sums are calculated for each digit (or byte) position.