Personalizable RAM Design Using Word Line Movement
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09
Personalizable random-access memory (RAM) devices used in state-of- the-art masterslices generally require in the order of four transistors per memory cell. This article concerns the design of a personalizable RAM in which only the two transistors already available in the full logic cell of an advanced design masterslice are required. The advanced design masterslice circuit shown in Fig. 1b uses a DTL (diode-transistor logic)-type circuit employing low barrier SBDs (Schottky barrier diodes) as the logic element. The memory cell uses two transistors for storage and employs four diodes for writing and reading through the bit lines. This is a difficult approach in comparison to the use of transistors, which have a base mode which can be lowered to shut off the transistor, as shown in Fig.