Browse Prior Art Database

DMA Memory Controller

IP.com Disclosure Number: IPCOM000062109D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Stucka, SE Wohler, WL [+details]

Abstract

This article describes a DMA controller that supports two addressing modes. The first mode is synchronous addressing by two input channels and the second mode, asynchronous, indirect addressing by a processor. Included are four options for disabling the channel accesses when address boundaries are encountered. The first mode of addressing, i.e., synchronous two channel, is the default mode. When the processor addresses the memory in the second mode, it overrides the first mode. The first mode supplies access to the memory on alternate cycles for each input channel. The controller alternates between the two channels while in the first mode even though every cycle allocated to a channel need not be utilized.