Browse Prior Art Database

Integrated Test Structure

IP.com Disclosure Number: IPCOM000062111D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Griffin, CW Lloyd, JR Wollman, LP [+details]

Abstract

This article describes a chip-test site structure which combines the numerous and formerly separate test sites for stud electromigration, interlevel and intralevel shorts, and opens into one test site for greater efficiency and reliability of test operation. Recent studies have shown that the problem of intralevel shorts due to electromigration is a very important one, especially in stud vias. The measurement of electromigration resistance in chain vias and the detection of via shorts to adjacent metal intralevel shorts have however, up to now, been conducted through separate tests at numerous test sites. The disclosed integrated test structure saves chip-test area by combining such requirements in the following manner. Fig. 1 shows vias deposited in a zig-zag pattern over the first and second level metallizations on a chip.