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Test Generation Algorithm to Propagate a CMOS Test Value

IP.com Disclosure Number: IPCOM000062117D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Shearon, PC [+details]

Abstract

An algorithm, when used in the computer program Enhanced Test Generation (ETG), increases test coverage and reduces running time in test generation for complementary metal-oxide-semiconductor (CMOS) logic circuits. During test generation on CMOS circuits containing sequential logic, a CMOS test value can propagate to the inputs of the block on which the test value originated. The algorithm makes it possible to propagate the CMOS test value through this block. Thus, it may be propagated to an observable point. The CMOS faults which this algorithm operates on are CMOS input inclusive, CMOS input exclusive, CMOS output transition to the controlled value, and CMOS output transition to the non-controlled value. These faults occur on "AND", "OR", "AI", and "OI" logic functions.